(1) Field of the Invention
This invention generally relates to fabrication of interconnect systems. More specifically, this invention relates to fabrication of via plugs and metal lines in interconnect systems.
(2) Background Information
Integrated circuits are generally manufactured starting from a substrate, typically made of silicon, that includes numerous active and passive devices such as transistors, capacitors and resistors. Such devices are initially isolated from one another but are later interconnected together to form functional circuits. Interconnects typically include metal lines which connect the various active and passive devices formed in the substrate. Interconnects also include vias which connect various layers of metal lines therebetween within the interconnect system. The quality of the interconnection of these devices drastically affects the performance and reliability of the fabricated integrated circuit. The process of connecting the devices by interconnects is known as metallization. Current semiconductor fabrication processes typically utilize Aluminum as metal for interconnects. Aluminum is superior to the other metals such as copper, gold, and silver, for example, in terms of relative ease of deposition and patterning onto the semiconductor substrate. However, Aluminum is not an ideal metal for interconnects because of its lower conductivity and poor electromigration characteristics relative to the other metals mentioned above.
As semiconductor devices shrink in size and processing speeds of these devices become faster due to advanced manufacturing techniques, the conductivity of the interconnect metal has become critical making metals such as copper highly desirable for metallization. The conductivity of the interconnect has become even more critical in the area of ULSI manufacturing where the width of the interconnects are within sub-half-micron ranges. Accordingly, metals with high conductivity, such as copper, have become highly desirable in interconnect systems. One process utilizing copper, known as xe2x80x9cDamascenexe2x80x9d, involves etching a dielectric layer such as silicon oxide, deposited on the surface of the substrate, to form patterned vias and oxide trenches. Copper is then deposited into the patterned vias and oxide trenches by way of sputtering or electroplating. Unwanted copper deposits are then removed from the surface of the substrate using conventional chemical-mechanical polishing (CMP) methods. However, this process is highly complicated and not readily controllable.
In processes, similar to the Damascene process, copper is deposited by electroplating. Using electroplating for metal deposition has its shortfalls. For example, copper tends to diffuse into the underlying and adjacent dielectric layer which usually results in a defective fabricated circuit. Therefore, typically, a barrier layer using compounds such as titanium-nitride needs to be formed on the substrate to prevent such diffusion. Unfortunately, copper does not adhere well to the barrier layer during electroplating resulting in poor interconnects. In ULSI manufacturing where the interconnects have widths in the sub-half-micron range, the poor adhesion results in defects which are usually fatal to the fabricated integrated circuit.
Consequently, the industry has turned to a number of copper electrolytic solutions to address this problem, a promising solution being copper cyanide in basic solution. However, if copper cyanide in basic solution accidentally comes in contact with an acidic solution, a byproduct of highly toxic cyanide gas is formed. Thus, the use of copper cyanide in basic solution is strongly discouraged in manufacturing for safety reasons. Accordingly, it is desirable to provide a metallization process using a desired metal having high conductivity, in an interconnect system, which overcomes the above mentioned shortcomings and is simple, economical, and highly controllable.
The present invention provides a method of forming an interconnect system. A barrier layer is formed onto a surface of a substrate that has at least one via. A conductive layer is formed onto the barrier layer. A photoresist layer is formed onto the conductive layer. The photoresist layer is patterned. A metal via plug is formed onto the at least one via. A metal line is formed onto said metal via plug. The layer of photoresist is removed. The conductive layer, not covered by the metal line, is removed.